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François R. Boyer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
    .NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:732-733 [Conf]
  2. Bill Pontikakis, François R. Boyer, Yvon Savaria
    Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:454-458 [Conf]
  3. James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
    ESys.Net: a new solution for embedded systems modeling and simulation. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:107-114 [Conf]
  4. François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer
    Optimal design of synchronous circuits using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:516-532 [Journal]
  5. Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
    A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:633-636 [Conf]
  6. Bill Pontikakis, François R. Boyer, Yvon Savaria
    A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  7. Implementation of a cycle by cycle variable speed processor. [Citation Graph (, )][DBLP]


  8. SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. [Citation Graph (, )][DBLP]


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