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François R. Boyer:
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 James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
.NET Framework  A Solution for the Next Generation Tools for SystemLevel Modeling and Simulation. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:732733 [Conf]
 Bill Pontikakis, François R. Boyer, Yvon Savaria
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. [Citation Graph (0, 0)][DBLP] IWSOC, 2005, pp:454458 [Conf]
 James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
ESys.Net: a new solution for embedded systems modeling and simulation. [Citation Graph (0, 0)][DBLP] LCTES, 2004, pp:107114 [Conf]
 François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer
Optimal design of synchronous circuits using software pipelining techniques. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:516532 [Journal]
 Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
A LowComplexity HighSpeed Clock Generator for Dynamic Frequency Scaling of FPGA and StandardCell Based Designs. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:633636 [Conf]
 Bill Pontikakis, François R. Boyer, Yvon Savaria
A 0.8V algorithmically defined buffer and ring oscillator lowenergy design for nanometer SoCs. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp: [Conf]
Implementation of a cycle by cycle variable speed processor. [Citation Graph (, )][DBLP]
SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. [Citation Graph (, )][DBLP]
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