Search the dblp DataBase

Publications of Author

1. Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung
   A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:384-389 [Conf]
   
2. Moo-Kyoung Chung, Chong-Min Kyung
   Improving Lookahead in Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction. [Citation Graph (0, 0)][DBLP]
   PADS, 2006, pp:11-18 [Conf]
   
3. Moo-Kyoung Chung, Chong-Min Kyung
   Improvement of Compiled Instruction Set Simulator by Increasing Flexibility a. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2004, pp:38-44 [Conf]
   
4. Moo-Kyoung Chung, Heejun Shim, Chong-Min Kyung
   Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2005, pp:158-164 [Conf]
   
5. Moo-Kyoung Chung, Chong-Min Kyung
   Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:2, pp:125-136 [Journal]
   
6. Sung-Joon Jang, Moo-Kyoung Chung, Jaemoon Kim, Chong-Min Kyung
   Cache Miss-Aware Dynamic Stack Allocation. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3494-3497 [Conf]
   
7. Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung
   A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [Citation Graph (0, 0)][DBLP]
   CoRR, 2007, v:0, n:, pp:- [Journal]
   
8. 
   Low latency variable length coding scheme for frame memory recompression. [Citation Graph (, )][DBLP]