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Luis Entrena-Arrontes: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
    Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:308-309 [Conf]
  2. Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes
    An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:218-219 [Conf]
  3. Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
    An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:397-402 [Conf]
  4. Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
    Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:43-48 [Conf]
  5. Luis Entrena-Arrontes, Kwang-Ting Cheng
    Combinational and sequential logic optimization by redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:909-916 [Journal]
  6. Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
    Techniques for Fast Transient Fault Grading Based on Autonomous Emulation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

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