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Didier Née: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Laurent Lopez, Jean Michel Portal, Didier Née
    A New Embedded Measurement Structure for eDRAM Capacitor. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:462-463 [Conf]
  2. B. Saillet, Jean Michel Portal, Didier Née
    Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:131-139 [Conf]
  3. Jean Michel Portal, L. Forli, Didier Née
    Floating-gate EEPROM cell: threshold voltage sensibility to geometry. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:557-560 [Conf]
  4. Jean Michel Portal, L. Forli, Didier Née
    Floating-gate EEPROM cell model based on MOS model 9. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:799-802 [Conf]
  5. L. Forli, Jean Michel Portal, Didier Née, B. Borot
    Infrastructure IP for Back-End Yield Improvement. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1129-1134 [Conf]
  6. Jean Michel Portal, H. Aziza, Didier Née
    EEPROM Memory: Threshold Voltage Built In Self Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:23-28 [Conf]
  7. Jean Michel Portal, L. Forli, H. Aziza, Didier Née
    An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:31-36 [Conf]
  8. Jean Michel Portal, L. Forli, H. Aziza, Didier Née
    An Automated Design Methodology for EEPROM Cell (ADE). [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:137-142 [Conf]
  9. Laurent Lopez, Jean Michel Portal, Didier Née
    A New Embedded Measurement Structure for eDRAM Capacitor [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  10. Jean Michel Portal, H. Aziza, Didier Née
    EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:33-42 [Journal]

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