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Kai-Yuan Chao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
    Flip-Flop and Repeater Insertion for Early Interconnect Planning. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:690-695 [Conf]
  2. Kai-Yuan Chao, D. F. Wong
    Layer assignment for high-performance multi-chip modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:680-685 [Conf]
  3. Kai-Yuan Chao, D. F. Wong
    Signal integrity optimization on the pad assignment for high-speed VLSI design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:720-725 [Conf]
  4. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    ECO algorithms for removing overlaps between power rails and signal wires. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:67-74 [Conf]
  5. Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
    Post-routing redundant via insertion and line end extension with via density consideration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:633-640 [Conf]
  6. Kai-Yuan Chao, D. F. Wong
    Thermal placement for high-performance multichip modules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:218-223 [Conf]
  7. Kai-Yuan Chao, D. F. Wong
    Floorplanning for Low Power Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:45-48 [Conf]
  8. Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
    An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:207-210 [Conf]
  9. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    An ECO algorithm for eliminating crosstalk violations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:41-46 [Conf]
  10. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:181-186 [Conf]
  11. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
    Simultaneous floor plan and buffer-block optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:694-703 [Journal]
  12. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    An ECO routing algorithm for eliminating coupling-capacitance violations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1754-1762 [Journal]
  13. Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
    Is your layout density verification exact?: a fast exact algorithm for density calculation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:19-26 [Conf]
  14. Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
    Dummy fill density analysis with coupling constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:3-10 [Conf]

  15. Coupling-aware Dummy Metal Insertion for Lithography. [Citation Graph (, )][DBLP]

  16. Spare-cell-aware multilevel analytical placement. [Citation Graph (, )][DBLP]

  17. Multi-threaded collision-aware global routing with bounded-length maze routing. [Citation Graph (, )][DBLP]

  18. Optimal post-routing redundant via insertion. [Citation Graph (, )][DBLP]

  19. Wire shaping is practical. [Citation Graph (, )][DBLP]

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