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Dionisios N. Pnevmatikatos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. G. Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis
    Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20014-20019 [Conf]
  2. Ioannis Sourdis, Dionisios N. Pnevmatikatos
    Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:258-267 [Conf]
  3. Giorgos Papadopoulos, Dionisios N. Pnevmatikatos
    Hashing + Memory = Low Cost, Exact Pattern Matching. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:39-44 [Conf]
  4. Ioannis Sourdis, Dionisios N. Pnevmatikatos
    Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:880-889 [Conf]
  5. Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stephan Wong, Stamatis Vassiliadis
    A Reconfigurable Perfect-Hashing Scheme for Packet Inspection. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:644-647 [Conf]
  6. Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
    Slice-processors: an implementation of operation-based prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:321-334 [Conf]
  7. Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi
    Streamlining Data Cache Access with Fast Address Calculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:369-380 [Conf]
  8. Dionisios N. Pnevmatikatos, Gurindar S. Sohi
    Guarded Executing and Branch Prediction in Dynamic ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:120-129 [Conf]
  9. Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi
    Control flow prediction for dynamic ILP processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:153-163 [Conf]
  10. Vassilis Dimopoulos, Giorgos Papadopoulos, Dionisios N. Pnevmatikatos
    On the Importance of Header Classification in HW/SW Network Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    Panhellenic Conference on Informatics, 2005, pp:661-671 [Conf]
  11. Apostolos Dollas, Nikolaos Aslanides, Stamatios Kavvadias, Euripides Sotiriades, Kyprianos Papademetriou, Dionisios N. Pnevmatikatos
    Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:17-23 [Conf]
  12. Ioannis Charitakis, Dionisios N. Pnevmatikatos, Evangelos P. Markatos, Kostas G. Anagnostakis
    Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:226-239 [Conf]
  13. Evangelos P. Markatos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Michail Flouris
    Secondary Storage Management for Web Proxies. [Citation Graph (0, 0)][DBLP]
    USENIX Symposium on Internet Technologies and Systems, 1999, pp:- [Conf]
  14. Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis
    Processing and Scheduling Components in an Innovative Network Processor Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:195-201 [Conf]
  15. Ioannis Sourdis, Vassilis Dimopoulos, Dionisios N. Pnevmatikatos, Stamatis Vassiliadis
    Packet pre-filtering for network intrusion detection. [Citation Graph (0, 0)][DBLP]
    ANCS, 2006, pp:183-192 [Conf]
  16. Dionisios N. Pnevmatikatos, Evangelos P. Markatos, Grigorios Magklis, Sotiris Ioannidis
    On using network RAM as a non-volatile buffer. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 1999, v:2, n:4, pp:295-303 [Journal]
  17. Dionisios N. Pnevmatikatos, Ioannis Sourdis, Kyriakos Vlachos
    An Efficient, Low-Cost I/O Subsystem for Network Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:56-64 [Journal]
  18. Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos
    PRO3: A Hybrid NPU Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:20-33 [Journal]
  19. Evangelos P. Markatos, Dionisios N. Pnevmatikatos, Michail Flouris, Manolis Katevenis
    Web-conscious storage management for web proxies. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2002, v:10, n:6, pp:735-748 [Journal]
  20. Kyriakos Vlachos, Theofanis Orphanoudakis, Yannis Papaefstathiou, Nikos A. Nikolaou, Dionisios N. Pnevmatikatos, George E. Konstantoulakis, Jorge-A. Sanchez-P.
    Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:3, pp:188-199 [Journal]
  21. Dionisios N. Pnevmatikatos, Aggelos Arelakis
    Variable-Length Hashing for Exact Pattern Matching. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  22. Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
    Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:41-47 [Conf]
  23. Vassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
    A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:186-193 [Conf]
  24. Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis
    Prototyping Efficient Interprocessor Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:26-33 [Conf]
  25. George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis
    Approaching Ideal NoC Latency with Pre-Configured Routes. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:153-162 [Conf]

  26. ReSim, a trace-driven, reconfigurable ILP processor simulator. [Citation Graph (, )][DBLP]

  27. Design and implementation of a database filter for BLAST acceleration. [Citation Graph (, )][DBLP]

  28. A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem. [Citation Graph (, )][DBLP]

  29. A rate-based prefiltering approach to blast acceleration. [Citation Graph (, )][DBLP]

  30. Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths. [Citation Graph (, )][DBLP]

  31. A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. [Citation Graph (, )][DBLP]

  32. FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. [Citation Graph (, )][DBLP]

  33. CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers. [Citation Graph (, )][DBLP]

  34. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  35. A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area. [Citation Graph (, )][DBLP]

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