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Ananta K. Majhi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
    Memory Testing Under Different Stress Conditions: An Industrial Evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:438-443 [Conf]
  2. Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger
    On Hazard-free Patterns for Fine-delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:213-222 [Conf]
  3. Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede
    Systematic Defects in Deep Sub-Micron Technologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:290-299 [Conf]
  4. S. Balajee, Ananta K. Majhi
    Automated AC (Timing) Characterization for Digital Circuit Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:374-377 [Conf]
  5. Ananta K. Majhi, Vishwani D. Agrawal
    Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:285-288 [Conf]
  6. Ananta K. Majhi, Vishwani D. Agrawal
    Tutorial: Delay Fault Models and Coverage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:364-369 [Conf]
  7. Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
    An efficient automatic test generation system for path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:161-165 [Conf]
  8. Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
    On test coverage of path delay faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:418-421 [Conf]
  9. Mohamed Azimane, Ananta K. Majhi
    New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:123-128 [Conf]
  10. Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg
    A New Algorithm for Dynamic Faults Detection in RAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:177-182 [Conf]
  11. Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger
    Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:345-350 [Conf]
  12. D. Arumi, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:145-150 [Conf]
  13. Bram Kruseman, Ananta K. Majhi, Guido Gronthoud
    On Performance Testing with Path Delay Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:29-34 [Conf]
  14. Rosa Rodríguez-Montañés, D. Arumi, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Full Open Defects in Interconnecting Lines. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:158-166 [Conf]
  15. Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
    Memory Testing Under Different Stress Conditions: An Industrial Evaluation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  16. Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik
    Line coverage of path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:610-614 [Journal]

  17. NIM- a noise index model to estimate delay discrepancies between silicon and simulation. [Citation Graph (, )][DBLP]


  18. Efficient Grouping of Fail Chips for Volume Yield Diagnostics. [Citation Graph (, )][DBLP]


  19. Impact of Temperature on Test Quality. [Citation Graph (, )][DBLP]


  20. Modeling Power Supply Noise in Delay Testing. [Citation Graph (, )][DBLP]


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