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Stefan Eichenberger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
    Memory Testing Under Different Stress Conditions: An Industrial Evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:438-443 [Conf]
  2. Stefan Eichenberger
    Design for Manufacturability - or the meaning of 'subtle'. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1316- [Conf]
  3. Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg
    An Effective Diagnosis Method to Support Yield Improvement. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:260-269 [Conf]
  4. Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger
    On Hazard-free Patterns for Fine-delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:213-222 [Conf]
  5. Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede
    Systematic Defects in Deep Sub-Micron Technologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:290-299 [Conf]
  6. Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger
    Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:345-350 [Conf]
  7. Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger
    Delay Defect Screening using Process Monitor Structures. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:43-52 [Conf]
  8. D. Arumi, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:145-150 [Conf]
  9. Rosa Rodríguez-Montañés, D. Arumi, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Full Open Defects in Interconnecting Lines. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:158-166 [Conf]
  10. Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker
    ITC 2003 Roundtable: Design for Manufacturability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:144-156 [Journal]
  11. Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen
    Memory Testing Under Different Stress Conditions: An Industrial Evaluation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  12. Impact of Temperature on Test Quality. [Citation Graph (, )][DBLP]


  13. Full Open Defects in Nanometric CMOS. [Citation Graph (, )][DBLP]


  14. Diagnosis of full open defects in interconnect lines with fan-out. [Citation Graph (, )][DBLP]


  15. Modeling Power Supply Noise in Delay Testing. [Citation Graph (, )][DBLP]


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