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Arindam Mallik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
    Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:618-623 [Conf]
  2. Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
    Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:770-779 [Conf]
  3. Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik
    Load elimination for low-power embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:282-285 [Conf]
  4. Arindam Mallik, Matthew C. Wildrick, Gokhan Memik
    Design and implementation of correlating caches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:58-61 [Conf]
  5. Arindam Mallik, Gokhan Memik
    A Case for Clumsy Packet Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:147-156 [Conf]
  6. Bin Lin, Arindam Mallik, Peter A. Dinda, Gokhan Memik, Robert P. Dick
    Power reduction through measurement and modeling of users and CPUs: summary. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:363-364 [Conf]
  7. Arindam Mallik, Gokhan Memik
    Low Power Correlating Caches for Network Processors. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:108-118 [Journal]

  8. PICSEL: measuring user-perceived performance to control dynamic frequency scaling. [Citation Graph (, )][DBLP]


  9. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. [Citation Graph (, )][DBLP]


  10. Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction. [Citation Graph (, )][DBLP]


  11. User- and process-driven dynamic voltage and frequency scaling. [Citation Graph (, )][DBLP]


  12. Variable latency caches for nanoscale processor. [Citation Graph (, )][DBLP]


  13. Automated task distribution in multicore network processors using statistical analysis. [Citation Graph (, )][DBLP]


  14. The user in experimental computer systems research. [Citation Graph (, )][DBLP]


  15. User-Driven Frequency Scaling. [Citation Graph (, )][DBLP]


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