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Publications of Author

1. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins
   Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1224-1229 [Conf]
   
2. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
   Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10296-10301 [Conf]
   
3. Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
   Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. [Citation Graph (0, 0)][DBLP]
   FPL, 2001, pp:264-274 [Conf]
   
4. Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein
   Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:622-625 [Conf]
   
5. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
   ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:61-70 [Conf]
   
6. Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei
   Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:106-111 [Conf]
   
7. Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
   Design Style Case Study for Embedded Multi Media Compute Nodes. [Citation Graph (0, 0)][DBLP]
   RTSS, 2004, pp:104-113 [Conf]
   
8. Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins
   Architecture Exploration for a Reconfigurable Architecture Template. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:2, pp:90-101 [Journal]
   
9. Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
   A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. [Citation Graph (0, 0)][DBLP]
   CASES, 2007, pp:229-237 [Conf]
   
10. Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Suk Jin Kim
    Hardware and a Tool Chain for ADRES. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:425-430 [Conf]
    
11. 
    Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays. [Citation Graph (, )][DBLP]