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Martijn T. Bennebroek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek
    Energy-efficient FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:42-47 [Conf]
  2. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  3. Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
    A Novel Toolset for the Development of FPGA-like Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:640-643 [Conf]
  4. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:393-396 [Conf]
  5. Martijn T. Bennebroek
    Validation of wire length distribution models on commercial designs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:41- [Conf]
  6. Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
    Astra: An Advanced Space-Time Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  7. Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek
    Communication-Centric SoC Debug Using Transactions. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:69-76 [Conf]
  8. Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek
    Transaction-Based Communication-Centric Debug. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:95-106 [Conf]

  9. A Novel Routing Architecture for Field-Programmable Gate-Arrays. [Citation Graph (, )][DBLP]


  10. Multiplexer-based routing fabric for reconfigurable logic. [Citation Graph (, )][DBLP]


  11. Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. [Citation Graph (, )][DBLP]


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