Search the dblp DataBase

Publications of Author

1. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
   MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:234-239 [Conf]
   
2. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
   MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:234-239 [Conf]
   
3. Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans
   Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:11122-11123 [Conf]
   
4. Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato
   FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1042-1046 [Conf]
   
5. Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans
   Remote and Partial Reconfiguration of FPGAs: Tools and Trends. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:177- [Conf]
   
6. Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes
   Infrastructure for dynamic reconfigurable systems: choices and trade-offs. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2006, pp:44-49 [Conf]
   
7. Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans
   A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:318-323 [Conf]
   
8. Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost
   HERMES: an infrastructure for low area overhead packet-switching networks on chip. [Citation Graph (0, 0)][DBLP]
   Integration, 2004, v:38, n:1, pp:69-93 [Journal]
   
9. Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes
   Reconfigurable Systems Enabled by a Network-on-Chip. [Citation Graph (0, 0)][DBLP]
   FPL, 2006, pp:1-4 [Conf]
   
10. Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes
    A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:23-30 [Conf]
    
11. Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
12. 
    Towards a unique FPGA-based identification circuit using process variations. [Citation Graph (, )][DBLP]
    
    
13. 
    Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. [Citation Graph (, )][DBLP]
    
    
14. 
    A simplified executable model to evaluate latency and throughput of networks-on-chip. [Citation Graph (, )][DBLP]
    
    
15. 
    Validation of executable application models mapped onto network-on-chip platforms. [Citation Graph (, )][DBLP]