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Publications of Author

1. Adam Morawiec, Raimund Ubar, Jaan Raik
   Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:743- [Conf]
   
2. Jaan Raik, Raimund Ubar
   Sequential Circuit Test Generation Using Decision Diagram Models. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:736-740 [Conf]
   
3. André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová
   Internet-Based Collaborative Test Generation with MOSCITO. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:221-226 [Conf]
   
4. Raimund Ubar, Jaan Raik, Adam Morawiec
   Cycle-based Simulation with Decision Diagrams. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:454-458 [Conf]
   
5. Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
   Layout to Logic Defect Analysis for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:35-40 [Conf]
   
6. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
   Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. [Citation Graph (0, 0)][DBLP]
   DELTA, 2002, pp:86-91 [Conf]
   
7. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
   Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP]
   DFT, 1997, pp:212-217 [Conf]
   
8. Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov
   An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. [Citation Graph (0, 0)][DBLP]
   DSD, 2005, pp:412-419 [Conf]
   
9. Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar
   Improved Fault Emulation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   DSD, 2005, pp:72-78 [Conf]
   
10. Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
    Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:79-82 [Conf]
    
11. Jaan Raik, Raimund Ubar, Taavi Viilukas
    High-Level Decision Diagram based Fault Models for Targeting FSMs. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:353-358 [Conf]
    
12. Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
    Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:332-344 [Conf]
    
13. Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe
    Evaluating Fault Emulation on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:354-363 [Conf]
    
14. Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider
    Web-Based Environment for Digital Electronics Test Tools. [Citation Graph (0, 0)][DBLP]
    Virtual Enterprises and Collaborative Networks, 2004, pp:435-442 [Conf]
    
15. Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:365-371 [Conf]
    
16. Raimund Ubar, Jaan Raik
    Efficient Hierarchical Approach to Test Generation for Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:189-196 [Conf]
    
17. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:12, pp:2023-2040 [Journal]
    
18. T. Cibáková, M. Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Hierarchical test generation for combinational circuits with real defects coverage. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:7, pp:1141-1149 [Journal]
    
19. Jaan Raik, Raimund Ubar, Vineeth Govind
    Test Configurations for Diagnosing Faulty Links in NoC Switches. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:29-34 [Conf]
    
20. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
    Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:131-136 [Conf]
    
21. Jaan Raik, Tanel Nõmmeots, Raimund Ubar
    A New Testability Calculation Method to Guide RTL Test Generation. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:71-82 [Journal]
    
22. 
    Parallel fault backtracing for calculation of fault coverage. [Citation Graph (, )][DBLP]
    
    
23. 
    Parallel X-fault simulation with critical path tracing technique. [Citation Graph (, )][DBLP]
    
    
24. 
    Code Coverage Analysis using High-Level Decision Diagrams. [Citation Graph (, )][DBLP]
    
    
25. 
    Web-Based Framework for Parallel Distributed Test. [Citation Graph (, )][DBLP]
    
    
26. 
    Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. [Citation Graph (, )][DBLP]
    
    
27. 
    Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. [Citation Graph (, )][DBLP]
    
    
28. 
    Fault Diagnosis in Integrated Circuits with BIST. [Citation Graph (, )][DBLP]
    
    
29. 
    Hierarchical Identification of Untestable Faults in Sequential Circuits. [Citation Graph (, )][DBLP]
    
    
30. 
    Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. [Citation Graph (, )][DBLP]
    
    
31. 
    Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. [Citation Graph (, )][DBLP]
    
    
32. 
    Structural fault collapsing by superposition of BDDs for test generation in digital circuits. [Citation Graph (, )][DBLP]
    
    
33. 
    Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. [Citation Graph (, )][DBLP]
    
    
34. 
    Evolutionary Approach to Test Generation for Functional BIST [Citation Graph (, )][DBLP]