The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Manoel Eusebio de Lima: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paulo Sérgio B. do Nascimento, Manoel Eusebio de Lima
    Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:375-380 [Conf]
  2. Remy Eskinazi Sant'Anna, Manoel Eusebio de Lima, Paulo Romero Martins Maciel
    A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:259- [Conf]
  3. Remy Eskinazi Sant'Anna, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Carlos A. Valderrama, Abel Guilhermino S. Filho, Paulo Sérgio B. do Nascimento
    A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:262- [Conf]
  4. Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusebio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino S. Filho
    A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:275- [Conf]
  5. Remy Eskinazi Sant'Anna, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Carlos A. Valderrama, Abel Guilhermino S. Filho, Paulo Sérgio B. do Nascimento
    A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  6. Julio A. de Oliveira Filho, Manoel Eusebio de Lima, Paulo Romero Martins Maciel
    Petri Net Based Interface Analysis for Fast IP-Core Integration. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:34-0 [Conf]
  7. Abner Barros, Pericles Lima, Juliana Xavier, Manoel E. Lima
    Teaching SoC Design in a Project-Oriented Course Based on Robotics. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:25-26 [Conf]
  8. A. G. Silva-Filho, F. R. Cordeiro, Remy Eskinazi Sant'Anna, Manoel Eusebio de Lima
    Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:75-83 [Conf]
  9. Paulo Sérgio B. do Nascimento, Manoel Eusebio de Lima, Stelita M. da Silva, Jordana L. Seixas
    Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:50-55 [Conf]
  10. Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusebio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino S. Filho
    A partial reconfigurable architecture for controllers based on Petri nets. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:16-21 [Conf]
  11. Abel Guilhermino S. Filho, Alejandro César Frery, Cristiano C. de Araujo, Haglay Alice, Jorge Cerqueira, Juliana A. Loureiro, Manoel Eusebio de Lima, Maria das Gracas S. Oliveira, Michelle Matos Horta
    Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:99-104 [Conf]
  12. Julio A. de Oliveira Filho, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Juliana Moura, Bruno Celso
    A Fast IP-Core Integration Methodology for SoC Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:131-136 [Conf]

  13. Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. [Citation Graph (, )][DBLP]


  14. Aquarius: a dynamically reconfigurable computing platform. [Citation Graph (, )][DBLP]


  15. Architecture for dense matrix multiplication on a high-performance reconfigurable system. [Citation Graph (, )][DBLP]


  16. Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. [Citation Graph (, )][DBLP]


  17. A Temporal Partitioning Methodology for Reconfigurable High Performance Computers. [Citation Graph (, )][DBLP]


Search in 0.019secs, Finished in 0.019secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002