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Y. Tsiatouhas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
    Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:112-116 [Conf]
  2. Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
    A Versatile Built-In Self-Test Scheme for Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:756- [Conf]
  3. Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas
    C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:155-163 [Conf]
  4. Y. Tsiatouhas, Th. Haniotakis
    A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:95-100 [Conf]
  5. Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
    On Path Delay Fault Testing of Multiplexer - Based Shifters. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:20-23 [Conf]
  6. A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky
    A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:52-57 [Conf]
  7. Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
    A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:56-60 [Conf]
  8. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos
    A Compact Built-In Current Sensor for IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:95-99 [Conf]
  9. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
    Concurrent Detection of Soft Errors Based on Current Monitoring. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:106-110 [Conf]
  10. Y. Tsiatouhas, S. Matakias, Angela Arapoyanni, Th. Haniotakis
    A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:12-16 [Conf]
  11. S. Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
    Fast, Parallel Two-Rail Code Checker with Enhanced Testability. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:149-156 [Conf]
  12. A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
    SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:145-148 [Conf]
  13. Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
    A Built-In Self-Test Scheme for Differential Ring Oscillators. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:448-452 [Conf]
  14. Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
    On Testability of Multiple Precharged Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:299-304 [Conf]
  15. Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
    An Embedded IDDQ Testing Architecture and Technique. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:442-0 [Conf]
  16. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
    Extending the Viability of IDDQ Testing in the Deep Submicron Era. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:100-105 [Conf]
  17. S. Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
    Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:293-296 [Conf]
  18. A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil
    The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:270-271 [Conf]
  19. G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni
    Management of charge pump circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:30, n:1, pp:91-101 [Journal]
  20. Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
    A new technique for IDDQ testing in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:31, n:2, pp:183-194 [Journal]
  21. Y. Tsiatouhas, Angela Arapoyanni
    High fan-in differential current mirror logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  22. Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
    Testable Designs of Multiple Precharged Domino Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:461-465 [Journal]

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