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T. W. Williams: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Petra Nordholz, Hartmut Grabinski, Dieter Treytnar, Jan Otterstedt, Dirk Niggemeyer, Uwe Arz, T. W. Williams
    Core Interconnect Testing Hazards. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:953-954 [Conf]
  2. T. W. Williams
    Testing in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:5-0 [Conf]
  3. J. C. Marshall, L. A. Ankeny, S. P. Clancy, J. H. Hall, J. H. Heiken, K. S. Holian, Stephen R. Lee, G. R. McNamara, J. W. Painter, M. E. Zander, Julian Cummings, Scott Haney, Steve Karmesin, William Humphrey, John Reynders, T. W. Williams, R. L. Graham
    Tecolote: An Object-Oriented Framework for Physics Development. [Citation Graph (0, 0)][DBLP]
    ECOOP Workshops, 1998, pp:458-459 [Conf]
  4. Jan Otterstedt, Dirk Niggemeyer, T. W. Williams
    Detection of CMOS address decoder open faults with March and pseudo random memory tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:53-62 [Conf]
  5. Petra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, T. W. Williams
    Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:28-33 [Conf]
  6. T. W. Williams, Stephen K. Sunter
    How Should Fault Coverage Be Defined? [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:325-328 [Conf]
  7. T. W. Williams
    IEEE-USA and the Issue of Member Choice. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:2, pp:123-124 [Journal]
  8. Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian
    A D&T Roundtable: Testing Mixed Logic and DRAM Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:2, pp:86-92 [Journal]

  9. Reaching the limits of low power design. [Citation Graph (, )][DBLP]

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