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Ondrej Novák: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ondrej Novák
    Comparison of Test Pattern Decompression Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11182-11183 [Conf]
  2. Jiri Jenícek, Ondrej Novák
    Test Pattern Compression Based on Pattern Overlapping. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:29-34 [Conf]
  3. Leos Kafka, Ondrej Novák
    FPGA-based Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:274-278 [Conf]
  4. Martin Stáva, Ondrej Novák
    HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:250-252 [Conf]
  5. Ondrej Novák, Jiri Nosek
    Test Pattern Decompression Using a Scan Chain. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:110-115 [Conf]
  6. Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský
    Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:300-308 [Conf]
  7. Martin Stáva, Ondrej Novák
    Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:251-256 [Conf]
  8. Ondrej Novák
    Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:303-320 [Conf]
  9. Ondrej Novák, Jirí Zahrádka, Zdenek Plíva
    COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:403-414 [Conf]
  10. Ondrej Novák, Jiri Nosek
    On Using Deterministic Test Sets in BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:127-132 [Conf]
  11. Ondrej Novák, Jiri Nosek
    Test-per-Clock Testing of the Circuits with Scan. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:90-0 [Conf]
  12. Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:262-265 [Journal]
  13. P. Golan, Ondrej Novák, Jan Hlavicka
    Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:4, pp:496-500 [Journal]

  14. Structural test of programmed FPGA circuits. [Citation Graph (, )][DBLP]


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