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Mark Zwolinski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi
    Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10596-10601 [Conf]
  2. Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç
    Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1133- [Conf]
  3. Zheng Rong Yang, Mark Zwolinski
    Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:244-248 [Conf]
  4. Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski
    Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:100-109 [Conf]
  5. Zheng Rong Yang, Mark Zwolinski
    Applying Mutual Information to Adaptive Mixture Models. [Citation Graph (0, 0)][DBLP]
    IDEAL, 2000, pp:250-255 [Conf]
  6. Petros Oikonomakos, Mark Zwolinski
    Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:185- [Conf]
  7. Petros Oikonomakos, Mark Zwolinski
    Foundation of Combined Datapath and Controller Self-checking Design. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:30-34 [Conf]
  8. Andrew D. Brown, Mark Zwolinski
    The continuous-discrete interface - What does this really mean? Modelling and simulation issues. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:894-897 [Conf]
  9. Vanco B. Litovski, Mark Zwolinski, Miona Andrejevic
    Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5182-5185 [Conf]
  10. Mark Zwolinski, Andrew D. Brown
    Behavioural modelling of analogue faults in VHDL-AMS - a case study. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:632-635 [Conf]
  11. Mark Zwolinski, R. W. Allen
    Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:451-454 [Conf]
  12. Yavuz Kiliç, Mark Zwolinski
    Process variation independent built-in current sensor for analogue built-in self-test. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:398-401 [Conf]
  13. Tom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski
    A General Purpose Network Solving System. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:147-156 [Conf]
  14. M. S. Gaur, Mark Zwolinski
    Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:901-906 [Conf]
  15. Karthik Baddam, Mark Zwolinski
    Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:854-862 [Conf]
  16. Keith R. Baker, Mark Zwolinski
    Interleaving: an additional topological compaction technique for Weinberger array generation. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:3, pp:169-176 [Journal]
  17. Andrew D. Brown, Mark Zwolinski
    Lee router modified for global routing. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1990, v:22, n:5, pp:296-300 [Journal]
  18. Andrew D. Brown, Mark Zwolinski, Ken G. Nichols, Tom J. Kazmierski
    Confidence in mixed-mode circuit simulation. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:2, pp:115-118 [Journal]
  19. Zheng Rong Yang, Mark Zwolinski
    Mutual Information Theory for Adaptive Mixture Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 2001, v:23, n:4, pp:396-403 [Journal]
  20. Petros Oikonomakos, Mark Zwolinski
    On the Design of Self-Checking Controllers with Datapath Interactions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1423-1434 [Journal]
  21. Petros Oikonomakos, Mark Zwolinski
    An Integrated High-Level On-Line Test Synthesis Tool. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2479-2491 [Journal]
  22. Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams
    Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:142-151 [Journal]
  23. Duncan Crutchley, Mark Zwolinski
    Globally convergent algorithms for DC operating point analysis of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2003, v:7, n:1, pp:2-10 [Journal]
  24. Mark Zwolinski
    A technique for transparent fault injection and simulation in VHDL. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:6, pp:797-804 [Journal]
  25. Mark Zwolinski, M. S. Gaur
    Integrating testability with design space exploration. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:5, pp:685-693 [Journal]
  26. Vanco B. Litovski, Miona Andrejevic, Mark Zwolinski
    Analogue electronic circuit diagnosis based on ANNs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:8, pp:1382-1391 [Journal]
  27. Arash Ahmadi, Mark Zwolinski
    Multiple-Width Bus Partitioning Approach to Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2994-2997 [Conf]
  28. Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod
    Dynamic Voltage Scaling Aware Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:15-20 [Conf]
  29. Himanshu Thapliyal, Mark Zwolinski
    Reversible Logic to Cryptographic Hardware: A New Paradigm [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]

  30. A communication infrastructure for a million processor machine. [Citation Graph (, )][DBLP]

  31. Divided Backend Duplication Methodology for Balanced Dual Rail Routing. [Citation Graph (, )][DBLP]

  32. Symbolic noise analysis approach to computational hardware optimization. [Citation Graph (, )][DBLP]

  33. Variation resilient adaptive controller for subthreshold circuits. [Citation Graph (, )][DBLP]

  34. A novel self-routing reconfigurable fault-tolerant cell array. [Citation Graph (, )][DBLP]

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