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Markus Olbrich: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Markus Olbrich, Erich Barke
    Placement Using a Localization Probability Model (LPM). [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1412- [Conf]
  2. Markus Olbrich, Achim Rein, Erich Barke
    An improved hierarchical classification algorithm for structural analysis of integrated circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:807- [Conf]
  3. Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke
    An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:79-88 [Conf]
  4. Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
    Robust wiring networks for DfY considering timing constraints. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:43-48 [Conf]
  5. Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten
    Routing of analog busses with parasitic symmetry. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:14-19 [Conf]
  6. Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke
    Wirelength Reduction Using 3-D Physical Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:453-462 [Conf]
  7. Andreas Hermann, Markus Olbrich, Erich Barke
    Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:13-18 [Conf]
  8. Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke
    Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:706-711 [Conf]
  9. M. Zhang, M. Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, E. Barke
    CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:243-248 [Conf]

  10. Analog circuit simulation using range arithmetics. [Citation Graph (, )][DBLP]

  11. Distribution arithmetic for stochastical analysis. [Citation Graph (, )][DBLP]

  12. A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. [Citation Graph (, )][DBLP]

  13. Considering possible opens in non-tree topology wire delay calculation. [Citation Graph (, )][DBLP]

  14. Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). [Citation Graph (, )][DBLP]

  15. Range Arithmetics to Speed up Reachability Analysis of Analog Systems. [Citation Graph (, )][DBLP]

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