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José Manuel Cazeaux: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:170-175 [Conf]
  2. Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
    Can Clock Faults be Detected Through Functional Test? [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:168-173 [Conf]
  3. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    The Other Side of the Timing Equation: a Result of Clock Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:169-177 [Conf]
  4. José Manuel Cazeaux, Martin Omaña, Cecilia Metra
    Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:17-24 [Conf]
  5. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    New High Speed CMOS Self-Checking Voter. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:58-66 [Conf]
  6. José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
    On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:23-28 [Conf]
  7. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:17-22 [Conf]
  8. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Self-Checking Voter for High Speed TMR Systems. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:377-389 [Journal]

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