The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Daniele Rossi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:170-175 [Conf]
  2. Martin Omaña, Daniele Rossi, Cecilia Metra
    High Speed and Highly Testable Parallel Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10608-10615 [Conf]
  3. Daniele Rossi, Carlo Steiner, Cecilia Metra
    Analysis of the impact of bus implemented EDCs on on-chip SSN. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:59-64 [Conf]
  4. Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
    Can Clock Faults be Detected Through Functional Test? [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:168-173 [Conf]
  5. Cecilia Metra, T. M. Mak, Daniele Rossi
    Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:63-70 [Conf]
  6. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    The Other Side of the Timing Equation: a Result of Clock Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:169-177 [Conf]
  7. Martin Omaña, Daniele Rossi, Cecilia Metra
    Fast and Low-Cost Clock Deskew Buffer. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:202-210 [Conf]
  8. Daniele Rossi, S. Cavallotti, Cecilia Metra
    Error Correcting Codes for Crosstalk Effect Minimization. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:257-0 [Conf]
  9. Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra
    Multiple Transient Faults in Logic: An Issue for Next Generation ICs. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:352-360 [Conf]
  10. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    New High Speed CMOS Self-Checking Voter. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:58-66 [Conf]
  11. Martin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra
    A Model for Transient Fault Propagation in Combinatorial Logic. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:111-0 [Conf]
  12. Daniele Rossi, V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra
    Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:8-12 [Conf]
  13. Daniele Rossi, V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra
    Power Consumption of Fault Tolerant Codes: the Active Elements. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:61-67 [Conf]
  14. Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra
    Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:135-140 [Conf]
  15. Daniele Rossi, Cecilia Metra, Bruno Riccò
    Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:221-225 [Conf]
  16. L. Di Silvio, Daniele Rossi, Cecilia Metra
    Crosstalk Effect Minimization for Encoded Busses. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:214-218 [Conf]
  17. André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra
    Coding Techniques for Low Switching Noise in Fault Tolerant Busses. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:183-189 [Conf]
  18. José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
    On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:23-28 [Conf]
  19. Daniele Rossi, Martin Omaña, Cecilia Metra, Andrea Pagni
    Checker No-Harm Alarm Robustness. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:275-280 [Conf]
  20. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:17-22 [Conf]
  21. Martin Omaña, Daniele Rossi, Cecilia Metra
    Novel Transient Fault Hardened Static Latch. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:886-892 [Conf]
  22. Daniele Rossi, Cecilia Metra, Bruno Riccò
    Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:27-31 [Conf]
  23. Martin Omaña, Daniele Rossi, Cecilia Metra
    Low Cost Scheme for On-Line Clock Skew Compensation. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:90-95 [Conf]
  24. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
    Exploiting ECC Redundancy to Minimize Crosstalk Impact. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:59-70 [Journal]
  25. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
    New ECC for Crosstalk Impact Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:340-348 [Journal]
  26. Martin Omaña, Daniele Rossi, Cecilia Metra
    Low Cost and High Speed Embedded Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:2, pp:153-164 [Journal]
  27. Cecilia Metra, Daniele Rossi, T. M. Mak
    Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:3, pp:415-428 [Journal]
  28. Vittorio Cortellessa, Pierluigi Pierini, Daniele Rossi
    Integrating Software Models and Platform Models for Performance Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2007, v:33, n:6, pp:385-401 [Journal]
  29. Daniele Rossi, Paolo Angelini, Cecilia Metra
    Configurable Error Control Scheme for NoC Signal Integrity. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:43-48 [Conf]
  30. Martin Omaña, Daniele Rossi, Cecilia Metra
    Latch Susceptibility to Transient Faults and New Hardening Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:9, pp:1255-1268 [Journal]
  31. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Self-Checking Voter for High Speed TMR Systems. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:377-389 [Journal]

  32. Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. [Citation Graph (, )][DBLP]


  33. Novel low-cost aging sensor. [Citation Graph (, )][DBLP]


  34. Novel High Speed Robust Latch. [Citation Graph (, )][DBLP]


  35. Simultaneous Switching Noise: The Relation between Bus Layout and Coding. [Citation Graph (, )][DBLP]


Search in 0.049secs, Finished in 0.051secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002