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Alberto García Ortiz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
    Estimation of Power Consumption in Encoded Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1103- [Conf]
  2. Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
    Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:381-390 [Conf]
  3. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
    Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1111-1114 [Conf]
  4. Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner
    Moment-Based Power Estimation in Very Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:107-112 [Conf]
  5. Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
    A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:323-328 [Conf]
  6. Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
    A linear model for high-level delay estimation in VDSM on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1078-1081 [Conf]
  7. Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
    Power reduction techniques for an OFDM burst synchronization core. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:265-268 [Conf]
  8. Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
    Design of an efficient OFDM burst synchronization scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:449-452 [Conf]
  9. Alberto García, Lukusa D. Kabulepa, Manfred Glesner
    Efficient estimation of signal transition activity in MAC architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:319-322 [Conf]
  10. José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
    Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:426-427 [Conf]
  11. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Inserting Data Encoding Techniques into NoC-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:299-304 [Conf]
  12. Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
    Switching Activity Estimation in Non-linear Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:269-278 [Conf]
  13. Tudor Murgan, P. B. Bacinschi, Alberto García Ortiz, Manfred Glesner
    Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:169-180 [Conf]
  14. Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner
    On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:819-828 [Conf]
  15. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Moment-Based Estimation of Switching Activity for Correlated Distributions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:859-868 [Conf]
  16. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:603-613 [Conf]
  17. Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner
    Prototyping of a High Performance Generic Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:42-47 [Conf]
  18. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:138-0 [Conf]
  19. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesus, Ocampo Hidalgo, Manfred Glesner
    Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:172-178 [Conf]
  20. Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Accurate capture of timing parameters in inductively-coupled on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:117-122 [Conf]
  21. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Transition Activity Estimation for General Correlated Data Distributions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:440-445 [Conf]
  22. Tudor Murgan, P. B. Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
    On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:242-254 [Conf]

  23. PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. [Citation Graph (, )][DBLP]


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