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Publications of Author

1. Saravanan Padmanaban, Spyros Tragoudas
   Exact Grading of Multiple Path Delay Faults. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:84-88 [Conf]
   
2. Saravanan Padmanaban, Spyros Tragoudas
   Non-Enumerative Path Delay Fault Diagnosis . [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10322-10327 [Conf]
   
3. Saravanan Padmanaban, Spyros Tragoudas
   Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:50-55 [Conf]
   
4. M. M. Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas
   Low power ATPG for path delay faults. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:389-392 [Conf]
   
5. Saravanan Padmanaban, Spyros Tragoudas
   An Adaptive Path Delay Fault Diagnosis Methodology. [Citation Graph (0, 0)][DBLP]
   ISQED, 2004, pp:491-496 [Conf]
   
6. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
   Exact path delay grading with fundamental BDD operations. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:642-651 [Conf]
   
7. Saravanan Padmanaban, Spyros Tragoudas
   A Critical Path Selection Method for Delay Testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:232-241 [Conf]
   
8. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
   Exact path delay fault coverage with fundamental ZBDD operations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:305-316 [Journal]
   
9. Saravanan Padmanaban, Spyros Tragoudas
   An implicit path-delay fault diagnosis methodology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1399-1408 [Journal]
   
10. Saravanan Padmanaban, Spyros Tragoudas
    Efficient identification of (critical) testable path delay faults using decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:77-87 [Journal]
    
11. Saravanan Padmanaban, Spyros Tragoudas
    Implicit grading of multiple path delay faults. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:346-361 [Journal]