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Luciano Volcan Agostini: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Roger Endrigo Carvalho Porto, Luciano Volcan Agostini
    Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:224-229 [Conf]
  2. Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva
    A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:210-213 [Conf]
  3. Luciano Volcan Agostini, Roger Porto, Sergio Bampi, Leandro Rosa, José Güntzel, Ivan Saraiva Silva
    High throughput architecture for H.264/AVC forward transforms block. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:320-323 [Conf]
  4. Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
    Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:445-446 [Conf]
  5. Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi
    Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:255-257 [Conf]
  6. Luciano Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi
    Parallel color space converters for JPEG image compression. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:4, pp:697-703 [Journal]
  7. Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana G. S. dos Santos, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  8. Luciano Volcan Agostini, Sergio Bampi
    FPGA Based Architectures for H. 264/AVC Video Compression Standard. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  9. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1617-1620 [Conf]
  10. Luciano Volcan Agostini, Roger Porto, José Güntzel, Ivan Saraiva Silva, Sergio Bampi
    High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  11. Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger E. Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Prototyping Strategy for a H.264/AVC Video Decoder. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:174-180 [Conf]
  12. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:52-57 [Conf]
  13. Luciano Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi
    Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:8, pp:487-497 [Journal]

  14. RIC Fast Adder and its Set Tolerant Implementation in FPGAs. [Citation Graph (, )][DBLP]


  15. Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction. [Citation Graph (, )][DBLP]


  16. A high throughput and low cost diamond search architecture for HDTV motion estimation. [Citation Graph (, )][DBLP]


  17. A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video. [Citation Graph (, )][DBLP]


  18. HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV. [Citation Graph (, )][DBLP]


  19. Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV. [Citation Graph (, )][DBLP]


  20. High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV. [Citation Graph (, )][DBLP]


  21. Transforms and quantization design targeting the H.264/AVC intra prediction constraints. [Citation Graph (, )][DBLP]


  22. High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV. [Citation Graph (, )][DBLP]


  23. A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder. [Citation Graph (, )][DBLP]


  24. Motion Compensation Hardware Accelerator Architecture for H.264/AVC. [Citation Graph (, )][DBLP]


  25. High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications. [Citation Graph (, )][DBLP]


  26. Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering order. [Citation Graph (, )][DBLP]


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