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Marco Re:
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Publications of Author
- Andrea Del Re, Alberto Nannarelli, Marco Re
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:686-687 [Conf]
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. [Citation Graph (0, 0)][DBLP] DFT, 2003, pp:401-408 [Conf]
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. [Citation Graph (0, 0)][DBLP] DFT, 2004, pp:158-164 [Conf]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
A Self Checking Reed Solomon Encoder: Design and Analysis. [Citation Graph (0, 0)][DBLP] DFT, 2005, pp:111-119 [Conf]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
FPGA oriented design of parity sharing RS codecs. [Citation Graph (0, 0)][DBLP] DFT, 2005, pp:259-265 [Conf]
- Marco Ottavi, Gian-Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. [Citation Graph (0, 0)][DBLP] DFT, 2001, pp:403-411 [Conf]
- Salvatore Pontarelli, Gian-Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology. [Citation Graph (0, 0)][DBLP] DFT, 2001, pp:455-460 [Conf]
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. [Citation Graph (0, 0)][DBLP] IOLTS, 2004, pp:141-148 [Conf]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Design of a Self Checking Reed Solomon Encoder. [Citation Graph (0, 0)][DBLP] IOLTS, 2005, pp:201-202 [Conf]
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Localization of Faults in Radix-n Signed Digit Adders. [Citation Graph (0, 0)][DBLP] IOLTS, 2006, pp:178-180 [Conf]
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
A fault tolerant hardware based file system manager for solid state mass memory. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:649-652 [Conf]
- Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1102-1105 [Conf]
- Gian-Carlo Cardarilli, Andrea Del Re, Marco Re
IP based reconfigurable digital platform for satellite communications. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:37-40 [Conf]
- Alberto Nannarelli, Gian-Carlo Cardarilli, Marco Re
Power-delay tradeoffs in residue number system. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:413-416 [Conf]
- Alberto Nannarelli, Marco Re, Gian-Carlo Cardarilli
Tradeoffs between residue number system and traditional FIR filters. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2001, pp:305-308 [Conf]
- Marco Re, Alberto Nannarelli, Gian-Carlo Cardarilli, Roberto Lojacono
FPGA realization of RNS to binary signed conversion architecture. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:350-353 [Conf]
- Alberto L. Sangiovanni-Vincentelli, Marco Re, Luciano Lavagno, Gian-Carlo Cardarilli, Roberto Lojacono
Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion. [Citation Graph (0, 0)][DBLP] ISCAS (2), 1999, pp:334-338 [Conf]
- Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Low-power implementation of polyphase filters in Quadratic Residue Number system. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:725-728 [Conf]
- Salvatore Pontarelli, Gian-Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano
A self-checking cell logic block for fault tolerant FPGAs. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2002, pp:477-480 [Conf]
- Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Power characterization of digital filters implemented on FPGA. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:801-804 [Conf]
- Gian-Carlo Cardarilli, Marco Re, Roberto Lojacono
VLSI implementation of a real time fuzzy processor. [Citation Graph (0, 0)][DBLP] Journal of Intelligent and Fuzzy Systems, 1998, v:6, n:3, pp:389-401 [Journal]
- Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2006, v:55, n:5, pp:534-540 [Journal]
- Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. [Citation Graph (0, 0)][DBLP] IOLTS, 2007, pp:194-196 [Conf]
- G. L. Bernocchi, Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
Low-power adaptive filter based on RNS components. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:3211-3214 [Conf]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Concurrent error detection in Reed Solomon decoders. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Gian-Carlo Cardarilli, Andrea Del Re, Marco Re, L. Simone
Optimized QPSK modulator for DVB-S applications. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Fault tolerant design of signed digit based FIR filters. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Analysis of Errors and Erasures in Parity Sharing RS Codecs. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2007, v:56, n:12, pp:1721-1726 [Journal]
- Gian-Carlo Cardarilli, A. Leandri, P. Marinucci, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
Design of a fault tolerant solid state mass memory. [Citation Graph (0, 0)][DBLP] IEEE Transactions on Reliability, 2003, v:52, n:4, pp:476-491 [Journal]
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
Concurrent Error Detection in Reed-Solomon Encoders and Decoders. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:842-846 [Journal]
- Gian-Carlo Cardarilli, Fabrizio Lombardi, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
A Comparative Evaluation of Designs for Reliable Memory Systems. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2005, v:21, n:4, pp:429-444 [Journal]
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. [Citation Graph (, )][DBLP]
A Novel Error Detection and Correction Technique for RNS Based FIR Filters. [Citation Graph (, )][DBLP]
Error Correction Codes for SEU and SEFI Tolerant Memory Systems. [Citation Graph (, )][DBLP]
Totally Fault Tolerant RNS Based FIR Filters. [Citation Graph (, )][DBLP]
Error detection in addition chain based ECC Point Multiplication. [Citation Graph (, )][DBLP]
ADAPTO: full-adder based reconfigurable architecture for bit level operations. [Citation Graph (, )][DBLP]
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