Search the dblp DataBase

Publications of Author

1. Teresa Riesgo, Yago Torroja, Eduardo de la Torre, J. Uceda
   Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:955-956 [Conf]
   
2. Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
   Flexible Core Reallocation for Virtex II Structures. [Citation Graph (0, 0)][DBLP]
   ERSA, 2005, pp:189-195 [Conf]
   
3. M. G. Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo
   Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1057-1061 [Conf]
   
4. Yaseer A. Durrani, Teresa Riesgo, Felipe Machado
   Power estimation for register transfer level by genetic algorithm. [Citation Graph (0, 0)][DBLP]
   ICINCO-RA, 2006, pp:527-530 [Conf]
   
5. Felipe Machado, Teresa Riesgo, Yago Torroja
   A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:645-657 [Conf]
   
6. Yaseer A. Durrani, Teresa Riesgo
   Power Macromodeling for High Level Power Estimation. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:232-236 [Conf]
   
7. Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
   Partial Reconfiguration for Core Reallocation and Flexible Communications. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:91-97 [Conf]
   
8. Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
   Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2005, pp:77-83 [Conf]
   
9. Eduardo de la Torre, Teresa Riesgo, J. Uceda, E. Macip, M. Rizzi
   Highly Configurable Control Boards: A Tool and a Design Experience. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2000, pp:174-0 [Conf]
   
10. José Bravo, Xavier Alamán, Teresa Riesgo
    Ubiquitous Computing and Ambient Intelligence: New Challenges for Computing. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:3, pp:233-235 [Journal]
    
11. Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo
    A Modular Architecture for Nodes in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:3, pp:328-339 [Journal]
    
12. Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly
    Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
    
13. Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
    Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:873-876 [Conf]
    
14. Yaseer A. Durrani, Ana Abril, Teresa Riesgo
    Efficient Power Macromodeling Technique for IP-Based Digital System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1145-1148 [Conf]
    
15. 
    Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. [Citation Graph (, )][DBLP]
    
    
16. 
    Generic Systolic Array for Run-Time Scalable Cores. [Citation Graph (, )][DBLP]
    
    
17. 
    A Fast Emulation-Based NoC Prototyping Framework. [Citation Graph (, )][DBLP]