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Josep Rius: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Josep Rius, Joan Figueras
    Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:543-548 [Conf]
  2. Bram Kruseman, Stefan van den Oetelaar, Josep Rius
    Comparison of IDDQ Testing and Very-Low Voltage Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:964-973 [Conf]
  3. Josep Rius, José Pineda de Gyvez, Maurice Meijer
    An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:187-196 [Conf]
  4. Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez
    Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:80-89 [Conf]
  5. Salvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
    BIST Technique by Equally Spaced Test Vector Sequences. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:206-216 [Conf]
  6. Josep Rius, Joan Figueras
    Detecting I/sub DDQ/ defective CMOS circuits by depowering. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:324-329 [Conf]
  7. Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
    IDDQ testing: state of the art and future trends. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:167-196 [Journal]
  8. Josep Rius, Maurice Meijer, José Pineda de Gyvez
    An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:80-86 [Journal]

  9. Analysis of the extra delay on interconnects caused by resistive opens and shorts. [Citation Graph (, )][DBLP]

  10. A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits. [Citation Graph (, )][DBLP]

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