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Publications of Author

1. Davor Runje, Mario Kovac
   Universal Strong Encryption FPGA Core Implementation. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:923-924 [Conf]
   
2. Mario Kovac, N. Ranganathan, M. Varanasi
   A Systolic Algorithm and Architecture for Galois Field Arithmetic. [Citation Graph (0, 0)][DBLP]
   IPPS, 1992, pp:283-288 [Conf]
   
3. Mario Kovac, N. Ranganathan
   ACE: A VLSI Chip for Galois Field GF (2^m) Based Exponentiation. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:291-296 [Conf]
   
4. Mario Kovac, N. Ranganathan
   JAGUAR: a high speed VLSI chip for JPEG image compression standard. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1995, pp:220-224 [Conf]
   
5. Mario Kovac, N. Ranganathan, M. Varanasi
   SIGMA: A VLSI Chip for Galois Field GF(2^m) Based Multiplication and Division. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1993, pp:25-30 [Conf]
   
6. Mario Kovac, N. Ranganathan, M. Varanasi
   SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:22-30 [Journal]
   
7. 
   Application of Dynamically Reconfigurable Processors in Digital Signal Processing. [Citation Graph (, )][DBLP]