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Isabel C. Teixeira: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira
    RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10994-10999 [Conf]
  2. Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, O. P. Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
    Embedded tutorial: TRP: integrating embedded test and ATE. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:34-37 [Conf]
  3. F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, I. M. Teixeira, João Paulo Teixeira
    Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:279-284 [Conf]
  4. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:295-300 [Conf]
  5. Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:109-116 [Conf]
  6. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:216-224 [Conf]
  7. Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:29-37 [Conf]
  8. P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Analysis of CMOS Analog Building Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:311-318 [Conf]
  9. C. Leong, P. Bento, P. Rodrigues, A. Trindade, J. C. Silva, P. Lousã, J. Rego, J. Nobre, J. Varela, João Paulo Teixeira, Isabel C. Teixeira
    Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:523-526 [Conf]
  10. Hugo Lérias, João Luz, Pedro Moura, Ana Mendes, Isabel C. Teixeira, João Paulo Teixeira
    Towards E-Management as Enabler for Accelerated Change. [Citation Graph (0, 0)][DBLP]
    ICEIS (2), 2001, pp:807-814 [Conf]
  11. O. P. Dias, Isabel C. Teixeira, João Paulo Teixeira, Leandro Buss Becker, Carlos Eduardo Pereira
    Optimizing Functional distribution in Complex System Design. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:75-86 [Conf]
  12. O. P. Dias, Isabel C. Teixeira, João Paulo Teixeira, Carlos Eduardo Pereira
    An OO Based Methodology for Real-Time HW/SW Systems Modeling. [Citation Graph (0, 0)][DBLP]
    DIPES, 1998, pp:213-222 [Conf]
  13. Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Modeling and Simulation of Time Domain Faults in Digital Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:5-10 [Conf]
  14. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:164-165 [Conf]
  15. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:197-201 [Conf]
  16. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:257-262 [Conf]
  17. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:281-286 [Conf]
  18. Leandro Buss Becker, Carlos Eduardo Pereira, O. P. Dias, Isabel C. Teixeira, João Paulo Teixeira
    MOSYS A Methodology for Automatic Object Identification from System Specification. [Citation Graph (0, 0)][DBLP]
    ISORC, 2000, pp:198-201 [Conf]
  19. O. P. Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Quality of Electronic Design: From Architectural Level to Test Coverage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:197-0 [Conf]
  20. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:207-212 [Conf]
  21. M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:720-728 [Conf]
  22. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:377-385 [Conf]
  23. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Defect-oriented test quality assessment using fault sampling and simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:35-42 [Conf]
  24. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
    RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:814-823 [Conf]
  25. M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Physical DFT for High Coverage of Realistic Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:642-651 [Conf]
  26. Marcelino B. Santos, F. M. Gongalves, Isabel C. Teixeira, João Paulo Teixeira
    Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:326-332 [Conf]
  27. Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
    Test preparation for high coverage of physical defects in CMOS digital ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:330-337 [Conf]
  28. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:167-172 [Conf]
  29. D. Barros Júnior, M. Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, J. P. Teixeira
    Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:349-363 [Journal]

  30. Programmable aging sensor for automotive safety-critical applications. [Citation Graph (, )][DBLP]


  31. Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. [Citation Graph (, )][DBLP]


  32. Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. [Citation Graph (, )][DBLP]


  33. A strategy for testability enhancement at layout level. [Citation Graph (, )][DBLP]


  34. Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. [Citation Graph (, )][DBLP]


  35. Built-in aging monitoring for safety-critical applications. [Citation Graph (, )][DBLP]


  36. Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. [Citation Graph (, )][DBLP]


  37. Data Acquisition Electronics for PET Mammography Imaging. [Citation Graph (, )][DBLP]


  38. On-Detector Electronics of the Clear PEM Scanner. [Citation Graph (, )][DBLP]


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