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João Paulo Teixeira: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira
    A Probabilistic Method for the Computation of Testability of RTL Constructs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:176-181 [Conf]
  2. Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira
    RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10994-10999 [Conf]
  3. Marcelino B. Santos, João Paulo Teixeira
    Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:549-0 [Conf]
  4. Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, O. P. Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
    Embedded tutorial: TRP: integrating embedded test and ATE. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:34-37 [Conf]
  5. José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira
    Probabilistic Testability Analysis and DFT Methods at RTL. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:216-217 [Conf]
  6. F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, I. M. Teixeira, João Paulo Teixeira
    Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:279-284 [Conf]
  7. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:295-300 [Conf]
  8. Antonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos
    On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:263-270 [Conf]
  9. Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:109-116 [Conf]
  10. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:216-224 [Conf]
  11. Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:29-37 [Conf]
  12. P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Analysis of CMOS Analog Building Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:311-318 [Conf]
  13. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
    Fault Modeling and Defect Level Projections in Digital ICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:436-442 [Conf]
  14. C. Leong, P. Bento, P. Rodrigues, A. Trindade, J. C. Silva, P. Lousã, J. Rego, J. Nobre, J. Varela, João Paulo Teixeira, Isabel C. Teixeira
    Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:523-526 [Conf]
  15. A. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
    Fault Simulation Using Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:839-848 [Conf]
  16. A. Parreira, João Paulo Teixeira, Marcelino B. Santos
    FPGAs BIST Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:333-343 [Conf]
  17. Hugo Lérias, João Luz, Pedro Moura, Ana Mendes, Isabel C. Teixeira, João Paulo Teixeira
    Towards E-Management as Enabler for Accelerated Change. [Citation Graph (0, 0)][DBLP]
    ICEIS (2), 2001, pp:807-814 [Conf]
  18. O. P. Dias, Isabel C. Teixeira, João Paulo Teixeira, Leandro Buss Becker, Carlos Eduardo Pereira
    Optimizing Functional distribution in Complex System Design. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:75-86 [Conf]
  19. O. P. Dias, Isabel C. Teixeira, João Paulo Teixeira, Carlos Eduardo Pereira
    An OO Based Methodology for Real-Time HW/SW Systems Modeling. [Citation Graph (0, 0)][DBLP]
    DIPES, 1998, pp:213-222 [Conf]
  20. Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Modeling and Simulation of Time Domain Faults in Digital Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:5-10 [Conf]
  21. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:164-165 [Conf]
  22. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:197-201 [Conf]
  23. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:257-262 [Conf]
  24. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:281-286 [Conf]
  25. Leandro Buss Becker, Carlos Eduardo Pereira, O. P. Dias, Isabel C. Teixeira, João Paulo Teixeira
    MOSYS A Methodology for Automatic Object Identification from System Specification. [Citation Graph (0, 0)][DBLP]
    ISORC, 2000, pp:198-201 [Conf]
  26. O. P. Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Quality of Electronic Design: From Architectural Level to Test Coverage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:197-0 [Conf]
  27. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:207-212 [Conf]
  28. M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:720-728 [Conf]
  29. F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira
    Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:620-628 [Conf]
  30. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:377-385 [Conf]
  31. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Defect-oriented test quality assessment using fault sampling and simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:35-42 [Conf]
  32. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
    RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:814-823 [Conf]
  33. M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Physical DFT for High Coverage of Realistic Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:642-651 [Conf]
  34. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
    IC Defects-Based Testability Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:500-509 [Conf]
  35. Fernando M. Gonçalves, João Paulo Teixeira
    Teaching Microelectronic-Based Integrated Systems Design and Test. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:65-66 [Conf]
  36. Diamantino Freitas, António Moura, Daniela Braga, Helder Ferreira, João Paulo Teixeira, Maria João Barros, Paulo Gouveia, Vagner Latsch
    A Project of Speech Input and Output in an E-commerce Application. [Citation Graph (0, 0)][DBLP]
    PorTAL, 2002, pp:141-150 [Conf]
  37. João Paulo Teixeira, Diamantino Freitas
    Evaluation of a Segmental Durations Model for TTS. [Citation Graph (0, 0)][DBLP]
    PROPOR, 2003, pp:40-48 [Conf]
  38. Daniela Braga, Diamantino Freitas, João Paulo Teixeira, Aldina Marques
    On the Use of Prosodic Labelling in Corpus-Based Linguistic Studies of Spontaneous Speech. [Citation Graph (0, 0)][DBLP]
    TSD, 2003, pp:388-393 [Conf]
  39. Fernando M. Gonçalves, João Paulo Teixeira
    Sampling Techniques of Non-Equally Probable Faults in VLSI System. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:283-288 [Conf]
  40. Marcelino B. Santos, F. M. Gongalves, Isabel C. Teixeira, João Paulo Teixeira
    Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:326-332 [Conf]
  41. Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
    Test preparation for high coverage of physical defects in CMOS digital ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:330-337 [Conf]
  42. A. Parreira, João Paulo Teixeira, Marcelino B. Santos
    Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  43. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
    Defect level evaluation in an IC design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1286-1293 [Journal]
  44. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:167-172 [Conf]

  45. Programmable aging sensor for automotive safety-critical applications. [Citation Graph (, )][DBLP]


  46. Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. [Citation Graph (, )][DBLP]


  47. Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. [Citation Graph (, )][DBLP]


  48. A strategy for testability enhancement at layout level. [Citation Graph (, )][DBLP]


  49. Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. [Citation Graph (, )][DBLP]


  50. Built-in aging monitoring for safety-critical applications. [Citation Graph (, )][DBLP]


  51. Controllability and observability in mixed signal cores. [Citation Graph (, )][DBLP]


  52. Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. [Citation Graph (, )][DBLP]


  53. Data Acquisition Electronics for PET Mammography Imaging. [Citation Graph (, )][DBLP]


  54. On-Detector Electronics of the Clear PEM Scanner. [Citation Graph (, )][DBLP]


  55. Signal Integrity Enhancement in Digital Circuits. [Citation Graph (, )][DBLP]


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