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Javid Jaffari: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:846-851 [Conf]
  2. A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz
    Leakage current reduction by new technique in standby mode. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:158-161 [Conf]
  3. Javid Jaffari, Mohab Anis
    Variability-aware device optimization under ION and leakage current constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:119-122 [Conf]
  4. Javid Jaffari, Mohab Anis
    Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:666-671 [Conf]
  5. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  6. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Scan-Based Structure with Reduced Static and Dynamic Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:477-487 [Journal]

  7. Practical Monte-Carlo based timing yield estimation of digital circuits. [Citation Graph (, )][DBLP]


  8. Correlation controlled sampling for efficient variability analysis of analog circuits. [Citation Graph (, )][DBLP]


  9. On efficient Monte Carlo-based statistical static timing analysis of digital circuits. [Citation Graph (, )][DBLP]


  10. Adaptive sampling for efficient failure probability analysis of SRAM cells. [Citation Graph (, )][DBLP]


  11. Variability-aware design of subthreshold devices. [Citation Graph (, )][DBLP]


  12. Switching activity reduction in low power Booth multiplier. [Citation Graph (, )][DBLP]


  13. Timing yield estimation of digital circuits using a control variate technique. [Citation Graph (, )][DBLP]


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