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José Silva Matos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Machado da Silva, J. Soeiro Duarte, José Silva Matos
    Mixed-Signal BIST Using Correlation and Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:744- [Conf]
  2. Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos
    A processor for testing mixed-signal cores in System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:184-191 [Conf]
  3. José Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos
    FAFNER-Accelerating Nesting Problems with FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:168-0 [Conf]
  4. José Carlos Alves, José Silva Matos
    RVC - A Reconfigurable Coprocessor for Vector Processing Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:258-259 [Conf]
  5. João Canas Ferreira, José Silva Matos
    A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:280-281 [Conf]
  6. João Canas Ferreira, José Silva Matos
    A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:886-890 [Conf]
  7. José Silva Matos, João Canas Ferreira, Ana C. Leão, José M. Silva
    An Approach to Testability Improvement of Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:161-164 [Conf]
  8. José M. M. Ferreira, Filipe S. Pinto, José Silva Matos
    A Boundary Scan Test Controller for Hierarchical BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:217-223 [Conf]
  9. José Silva Matos, Ana C. Leão, João Canas Ferreira
    Control and Observation of Analog Nodes in Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:323-331 [Conf]
  10. José Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves
    Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:509-517 [Conf]
  11. José Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos
    ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order Moments. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1996, pp:96-107 [Conf]
  12. José Silva Matos
    Computer Organisation, Programming and Benchmarking - Introduction. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:331-333 [Conf]

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