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Publications of Author

1. Naran Sirisantana, Kaushik Roy
   Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:11160-11161 [Conf]
   
2. Naran Sirisantana, Liqiong Wei, Kaushik Roy
   High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. [Citation Graph (0, 0)][DBLP]
   ICCD, 2000, pp:227-0 [Conf]
   
3. Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
   Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2001, pp:267-270 [Conf]
   
4. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
   Synthesis of Selectively Clocked Skewed Logic Circuits. [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:229-234 [Conf]
   
5. Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy
   Enhancing Yield at the End of the Technology Roadmap. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2004, v:21, n:6, pp:563-571 [Journal]
   
6. Naran Sirisantana, Kaushik Roy
   Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2004, v:21, n:1, pp:56-63 [Journal]
   
7. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
   Synthesis of skewed logic circuits. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:205-228 [Journal]
   
8. Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
   Skewed CMOS: noise-tolerant high-performance low-power static circuit family. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:469-476 [Journal]