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Mark Bernd Kulaczewski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch
    HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20008-20013 [Conf]
  2. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch
    HiBRID-SoC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:101-104 [Conf]
  3. Mark Bernd Kulaczewski, Howard Jay Siegel
    Implementations of a Feature-Based Visual Tracking Algorithm on Two MIMD Machines Mark Bernd. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:422-430 [Conf]
  4. Mark Bernd Kulaczewski, Howard Jay Siegel
    SIMD and Mixed-Mode Implementations of a Visual Tracking Algorithm. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:716-720 [Conf]
  5. Howard Jay Siegel, Tracy D. Braun, Henry G. Dietz, Mark Bernd Kulaczewski, Muthucumaru Maheswaran, Pierre H. Pero, Janet M. Siegel, John John E. So, Min Tan, Mitchell D. Theys, Lee Wang
    The PASM Project: A Study of Reconfigurable Parallel Computing. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1996, pp:529-536 [Conf]
  6. Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch
    CHIPDESIGN - A Novel Project-oriented Microelectronics Course. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:71-72 [Conf]
  7. Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch
    HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:155-160 [Conf]
  8. Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, A. Dehnhardt, Peter Pirsch
    HIBRID-SOC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:55-61 [Journal]

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