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Ingmar Neumann: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas VanGinneken
    Improving Placement under the Constant Delay Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:677-682 [Conf]
  2. Ingmar Neumann, Wolfgang Kunz
    Placement Driven Retiming with a Coupled Edge Timing Model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:95-102 [Conf]
  3. Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz
    Cell replication and redundancy elimination during placement for cycle time optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:25-30 [Conf]
  4. Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
    Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:350-353 [Conf]
  5. Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz
    Cycle time optimization by timing driven placement with simultaneous netlist transformations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:359-362 [Conf]
  6. Ingmar Neumann, Wolfgang Kunz
    Tight coupling of timing-driven placement and retiming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:351-354 [Conf]
  7. Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
    Accelerating Retiming Under the Coupled-Edge Timing Model. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:135-140 [Conf]
  8. Ingmar Neumann, Hans-Ulrich Post
    Timing driven cell replication during placement for cycle time optimization. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:2, pp:131-141 [Journal]
  9. Ingmar Neumann, Wolfgang Wilhelmi
    A Parallel Algorithm for Achieving the Smith Normal Form of an Integer Matrix. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1996, v:22, n:10, pp:1399-1412 [Journal]
  10. Ingmar Neumann, Wolfgang Kunz
    Layout driven retiming using the coupled edge timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:825-835 [Journal]

  11. The AutoSUN Verification Environment. [Citation Graph (, )][DBLP]


  12. Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). [Citation Graph (, )][DBLP]


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