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Publications of Author

1. Hua Tang, Ying Wei, Alex Doboli
   MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:264-269 [Conf]
   
2. Ying Wei, Hua Tang, Alex Doboli
   Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:393-398 [Conf]
   
3. Hua Tang, Hui Zhang, Alex Doboli
   Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2003, pp:207-210 [Conf]
   
4. Piyush Maheshwari, Hua Tang, Roger Liang
   Enhancing Web Services with Message-Oriented Middleware. [Citation Graph (0, 0)][DBLP]
   ICWS, 2004, pp:524-531 [Conf]
   
5. Hua Tang, Alex Doboli
   Parameter domain pruning for improving convergence of synthesis algorithms. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1282-1285 [Conf]
   
6. Nattawut Thepayasuwan, Hua Tang, Alex Doboli
   An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:629-632 [Conf]
   
7. Hui Zhang, Preethi Karthik, Hua Tang, Alex Doboli
   An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:5629-5632 [Conf]
   
8. Hua Tang, Hui Zhang, Alex Doboli
   Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2003, pp:266-271 [Conf]
   
9. Hua Tang, Alex Doboli
   Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. [Citation Graph (0, 0)][DBLP]
   IWLS, 2002, pp:41-44 [Conf]
   
10. Pei Wang, Hua Tang, Heidi Zhang, Jeffrey Whiteaker, Amanda G. Paulovich, Martin McIntosh
    Normalization Regarding Non-Random Missing Values in High-Throughput Mass Spectrometry Data. [Citation Graph (0, 0)][DBLP]
    Pacific Symposium on Biocomputing, 2006, pp:315-326 [Conf]
    
11. Hua Tang, Alex Doboli
    High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:597-607 [Journal]
    
12. Hua Tang, Hui Zhang, Alex Doboli
    Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1421-1440 [Journal]
    
13. Yong-Bing Shi, Yin-Cai Tang, Hua Tang, Ling-Liu Gong, Li Xu
    Two Classes of Simple MCD Graphs. [Citation Graph (0, 0)][DBLP]
    CJCDGCGT, 2005, pp:177-188 [Conf]
    
14. Hui Zhang, Simona Doboli, Hua Tang, Alex Doboli
    Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:193-208 [Journal]
    
15. Robert A. Morris, Jacob K. Asiedu, William A. Haber, Fred SaintOurs, Robert D. Stevenson, Hua Tang
    Database-backed decision trees with application to biological informatics. [Citation Graph (0, 0)][DBLP]
    J. Intell. Inf. Syst., 2007, v:29, n:1, pp:25-38 [Journal]
    
16. 
    A Web-Based Data Mining System for Forest Resource Planning System. [Citation Graph (, )][DBLP]
    
    
17. 
    A simple technique to reduce clock jitter effects in continuous-time delta-sigma modulators. [Citation Graph (, )][DBLP]
    
    
18. 
    Post-optimization of Delta-Sigma modulators considering circuit non-idealities. [Citation Graph (, )][DBLP]
    
    
19. 
    Analog design retargeting by design knowledge reuse and circuit synthesis. [Citation Graph (, )][DBLP]
    
    
20. 
    Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators. [Citation Graph (, )][DBLP]
    
    
21. 
    Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications. [Citation Graph (, )][DBLP]
    
    
22. 
    Low power embedded speech recognition system based on a MCU and a coprocessor. [Citation Graph (, )][DBLP]