The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Nattawut Thepayasuwan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nattawut Thepayasuwan, Alex Doboli
    Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:108-113 [Conf]
  2. Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Eugene A. Feinberg
    A continuous time markov decision process based on-chip buffer allocation methodology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:345-348 [Conf]
  3. Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli
    Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:126-133 [Conf]
  4. Nattawut Thepayasuwan, Alex Doboli
    Hardware-Software Co-Design of Resource Constrained Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2004, pp:818-823 [Conf]
  5. Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli
    Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1044-1047 [Conf]
  6. Nattawut Thepayasuwan, Hua Tang, Alex Doboli
    An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:629-632 [Conf]
  7. Nattawut Thepayasuwan, Alex Doboli
    OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:264-265 [Conf]
  8. Nattawut Thepayasuwan, Alex Doboli
    A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:57-60 [Conf]
  9. Nattawut Thepayasuwan, Alex Doboli
    Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:525-538 [Journal]

Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002