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Maria K. Michael: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Spyros Tragoudas, Maria K. Michael
    ATPG Tools for Delay Faults at the Functional Level. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:631-0 [Conf]
  2. Kyriakos Christou, Maria K. Michael, Spyros Tragoudas
    Implicit Critical PDF Test Generation with Maximal Test Efficiency. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:50-58 [Conf]
  3. Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
    Test set enhancement for quality transition faults using function-based methods. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:182-187 [Conf]
  4. Spyros Tragoudas, Maria K. Michael
    Functional ATPG for Delay Faults. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:16-19 [Conf]
  5. Maria K. Michael, Kyriakos Christou, Spyros Tragoudas
    Towards finding path delay fault tests with high test efficiency using ZBDDs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:464-467 [Conf]
  6. Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
    Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:43-50 [Conf]
  7. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Evaluation of Collapsing Methods for Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:439-444 [Conf]
  8. Maria K. Michael, Stelios Neophytou, Spyros Tragoudas
    Functions for Quality Transition Fault Tests. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:327-332 [Conf]
  9. Maria K. Michael, Spyros Tragoudas
    ATPG for Path Delay Faults without Path Enumeration. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:384-0 [Conf]
  10. Maria K. Michael, Spyros Tragoudas
    Generation of Hazard Identification Functions. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:419-424 [Conf]
  11. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
    Exact path delay grading with fundamental BDD operations. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:642-651 [Conf]
  12. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Accelerating Diagnosis via Dominance Relations between Sets of Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:219-224 [Conf]
  13. Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas
    A unified framework for generating all propagation functions for logic errors and events. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:980-986 [Journal]
  14. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
    Exact path delay fault coverage with fundamental ZBDD operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:305-316 [Journal]
  15. Maria K. Michael, Spyros Tragoudas
    ATPG tools for delay faults at the functional level. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:33-57 [Journal]
  16. Maria K. Michael, Spyros Tragoudas
    Function-based compact test pattern generation for path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:996-1001 [Journal]
  17. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Sub-faults identification for collapsing in diagnosis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  18. Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits. [Citation Graph (, )][DBLP]


  19. Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning. [Citation Graph (, )][DBLP]


  20. Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. [Citation Graph (, )][DBLP]


  21. Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation. [Citation Graph (, )][DBLP]


  22. Two New Methods for Accurate Test Set Relaxation via Test Set Replacement. [Citation Graph (, )][DBLP]


  23. A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures. [Citation Graph (, )][DBLP]


  24. On the Relaxation of n-detect Test Sets. [Citation Graph (, )][DBLP]


  25. A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. [Citation Graph (, )][DBLP]


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