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José Pineda de Gyvez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Josep Rius Vázquez, José Pineda de Gyvez
    Power Supply Noise Monitor for Signal Integrity Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1406-1407 [Conf]
  2. Madhuban Kishor, José Pineda de Gyvez
    Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:349-357 [Conf]
  3. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  4. Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick
    Encoded-Low Swing Technique for Ultra Low Power Interconnect. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:240-251 [Conf]
  5. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:393-396 [Conf]
  6. Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez
    A Universal Interface Between PC and Neural Networks Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1169-1172 [Conf]
  7. Chi-Chien Lee, José Pineda de Gyvez
    Single-Layer CNN Simulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:217-220 [Conf]
  8. Chi-Chien Lee, José Pineda de Gyvez
    Time-Mulitplexing CNN Simulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:407-410 [Conf]
  9. Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
    Limits to performance spread tuning using adaptive voltage and body biasing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:5-8 [Conf]
  10. Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
    Glitch-free discretely programmable clock generation on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1839-1842 [Conf]
  11. Oscar Moreira-Tamayo, José Pineda de Gyvez
    Time Domain Analog Wavelet Transform in Real-Time. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1640-1643 [Conf]
  12. John Willis, José Pineda de Gyvez
    Behavioral Testing of Cellular Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:229-232 [Conf]
  13. A. Dornbusch, José Pineda de Gyvez
    Chaotic generation of PN sequences: a VLSI implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:454-457 [Conf]
  14. O. A. Gonzalez, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio
    CMOS cryptosystem using a Lorenz chaotic oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:442-445 [Conf]
  15. Maurice Meijer, José Pineda de Gyvez, Ralph Otten
    On-chip digital power supply control for system-on-chip applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:311-314 [Conf]
  16. Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
    Technology exploration for adaptive power and frequency scaling in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:14-19 [Conf]
  17. José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
    VDD Ramp Testing for RF Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:651-658 [Conf]
  18. José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller
    Power Supply Ramping for Quasi-static Testing of PLLs. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:980-987 [Conf]
  19. Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
    AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1006-1015 [Conf]
  20. Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio
    An Analog Integrated Circuit Design Laboratory. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:91-92 [Conf]
  21. Josep Rius, José Pineda de Gyvez, Maurice Meijer
    An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:187-196 [Conf]
  22. Phillip Christie, José Pineda de Gyvez
    Pre-layout prediction of interconnect manufacturability. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:167-173 [Conf]
  23. José Pineda de Gyvez
    Yield modeling and BEOL fundamentals. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:135-163 [Conf]
  24. Rohini Krishnan, José Pineda de Gyvez
    Low Energy Switch Block For FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:209-214 [Conf]
  25. José Pineda de Gyvez, Rosa Rodríguez-Montañés
    Threshold Voltage Mismatch (DeltaVT) Fault Modeling. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:145-150 [Conf]
  26. José Pineda de Gyvez, Eric van de Wetering
    Average Leakage Current Estimation of CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:375-379 [Conf]
  27. Josep Rius Vázquez, José Pineda de Gyvez
    Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:53-58 [Conf]
  28. Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez
    Resistance Characterization for Weak Open Defects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:18-26 [Journal]
  29. Apollo Q. Fong, Ajay Kanji, José Pineda de Gyvez
    Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1996, v:2, n:4, pp:231-239 [Journal]
  30. José Pineda de Gyvez, Chennian Di
    IC defect sensitivity for footprint-type spot defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:638-658 [Journal]
  31. José Pineda de Gyvez, Jochen A. G. Jess
    On the design and implementation of a wafer yield editor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:920-925 [Journal]
  32. Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
    Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1301-1306 [Conf]
  33. Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
    Testing and Diagnosis of Power Switches in SOCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:145-150 [Conf]
  34. Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio
    Time multiplexed color image processing based on a CNN with cell-state outputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:314-322 [Journal]
  35. Phillip Christie, José Pineda de Gyvez
    Prelayout interconnect yield prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:55-59 [Journal]
  36. Josep Rius, Maurice Meijer, José Pineda de Gyvez
    An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:80-86 [Journal]
  37. José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
    Multi-VDD Testing for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:311-322 [Journal]
  38. Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud
    Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:399-409 [Journal]

  39. Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. [Citation Graph (, )][DBLP]


  40. Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. [Citation Graph (, )][DBLP]


  41. Calibration and Debugging of Multi-step Analog to Digital Converters. [Citation Graph (, )][DBLP]


  42. Body bias driven design synthesis for optimum performance per area. [Citation Graph (, )][DBLP]


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