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Vivekananda M. Vedula: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vivekananda M. Vedula, Jacob A. Abraham
    FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:730-735 [Conf]
  2. Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham
    Native Mode Functional Self-Test Generation for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:280-285 [Conf]
  3. Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
    Verifying Properties Using Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:194-202 [Conf]
  4. Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
    Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:243-248 [Conf]
  5. Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham
    Program Slicing for ATPG-Based Property Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:591-596 [Conf]
  6. K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
    Controllability-driven Power Virus Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:407-412 [Conf]
  7. Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
    Program Slicing for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:237-246 [Conf]
  8. K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
    Power Virus Generation Using Behavioral Models of Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:35-42 [Conf]

  9. A Scalable Symbolic Simulator for Verilog RTL. [Citation Graph (, )][DBLP]

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