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Francisco-Javier Veredas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
    Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:36-41 [Conf]
  2. Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein
    Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:622-625 [Conf]
  3. Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei
    Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:106-111 [Conf]
  4. Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
    Regular Routing Architecture for a LUT-based MPGA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:257-262 [Conf]
  5. Francisco-Javier Veredas, Jordi Carrabina
    Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:666-673 [Conf]
  6. Francisco-Javier Veredas, Hans-Jörg Pfleiderer
    Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  7. Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
    LUT-based MPGAs for fast turnaround time conversion flow. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

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