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Michele Stucchi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe
    Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1113- [Conf]
  2. Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene
    Statistically Aware SRAM Memory Array Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:25-30 [Conf]
  3. Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex
    Interconnect width selection for deep submicron designs using the table lookup method. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:41-44 [Conf]
  4. Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex
    Impact of interconnect resistance increase on system performance of low power and high performance designs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:85-90 [Conf]
  5. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Global interconnect trade-off for technology over memory modules to application level: case study. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:125-132 [Conf]
  6. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Interconnect exploration for future wire dominated technologies. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:105-106 [Conf]

  7. A tool flow for predicting system level timing failures due to interconnect reliability degradation. [Citation Graph (, )][DBLP]


  8. Impact of 3D design choices on manufacturing cost. [Citation Graph (, )][DBLP]


  9. 3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). [Citation Graph (, )][DBLP]


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