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Yu-Shen Yang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:996-1001 [Conf]
  2. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Diagnosis and Correction in High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:423-430 [Conf]
  3. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:54-59 [Conf]
  4. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction error modeling and automated model debugging in high-performance custom designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:763-776 [Journal]

  5. Automating Logic Rectification by Approximate SPFDs. [Citation Graph (, )][DBLP]


  6. Automated data analysis solutions to silicon debug. [Citation Graph (, )][DBLP]


  7. Sequential logic rectifications with approximate SPFDs. [Citation Graph (, )][DBLP]


  8. On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. [Citation Graph (, )][DBLP]


  9. Automated silicon debug data analysis techniques for a hardware data acquisition environment. [Citation Graph (, )][DBLP]


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