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Paul J. Thadikaran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:996-1001 [Conf]
  2. Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel
    Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:340-349 [Conf]
  3. Sreejit Chakravarty, Paul J. Thadikaran
    A Study of IDDQ Subset Selection Algorithms for Bridging Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:403-412 [Conf]
  4. Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
    Techniques to Reduce Data Volume and Application Time for Transition Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:983-992 [Conf]
  5. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Diagnosis and Correction in High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:423-430 [Conf]
  6. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:54-59 [Conf]
  7. Goutam Debnath, Paul J. Thadikaran
    Design Challenges for High Performance Nano-Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:12-13 [Conf]
  8. Paul J. Thadikaran, Sreejit Chakravarty
    Fast Algorithms for Computer IDDQ Tests for Combination Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:103-106 [Conf]
  9. Debashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran
    Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:97-102 [Conf]
  10. Sreejit Chakravarty, Paul J. Thadikaran
    Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1131-1140 [Journal]
  11. Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
    Efficient techniques for transition testing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:258-278 [Journal]
  12. Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel
    Algorithms to compute bridging fault coverage of IDDQ test sets. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:281-305 [Journal]
  13. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction error modeling and automated model debugging in high-performance custom designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:763-776 [Journal]

  14. Design for Manufacturability and Reliability in Nano Era. [Citation Graph (, )][DBLP]


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