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Publications of Author

1. Kamran Zarrineh, Shambhu J. Upadhyaya
   On Programmable Memory Built-In Self Test Architectures. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:708-713 [Conf]
   
2. Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams
   Defect Analysis and a New Fault Model for Multi-port SRAMs. [Citation Graph (0, 0)][DBLP]
   DFT, 2001, pp:366-374 [Conf]
   
3. Kamran Zarrineh, Shambhu J. Upadhyaya
   Programmable Memory BIST and a New Synthesis Framework. [Citation Graph (0, 0)][DBLP]
   FTCS, 1999, pp:352-355 [Conf]
   
4. Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer
   A Design For Test Perspective on I/O Management. [Citation Graph (0, 0)][DBLP]
   ICCD, 1996, pp:46-0 [Conf]
   
5. Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
   Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
   ICCD, 2001, pp:526-529 [Conf]
   
6. Kamran Zarrineh, Shambhu J. Upadhyaya
   A design for test perspective on memory synthesis. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:101-104 [Conf]
   
7. Vivek Chickermane, Kamran Zarrineh
   Addressing Early Design-For-Test Synthesis in a Production Environment. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:246-255 [Conf]
   
8. Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod
   The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:998-1007 [Conf]
   
9. Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor
   Self test architecture for testing complex memory structures. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:547-556 [Conf]
   
10. Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
    A new framework for generating optimal March tests for memory arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:73-0 [Conf]
    
11. Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo
    Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2000, pp:119-124 [Conf]
    
12. Kamran Zarrineh, Shambhu J. Upadhyaya
    A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:391-397 [Conf]
    
13. Kamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III
    Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:98-105 [Conf]
    
14. Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane
    System-on-Chip Testability Using LSSD Scan Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:83-97 [Journal]
    
15. Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
    Automatic generation and compaction of March tests for memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:845-857 [Journal]
    
16. 
    Design for Test Challenges of High Performance/Low Power Microprocessors. [Citation Graph (, )][DBLP]