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Matthew M. Ziegler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Matthew M. Ziegler, Mircea R. Stan
    A Unified Design Space for Regular Parallel Prefix Adders. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1386-1387 [Conf]
  2. Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu (Jerry) Qi, Mircea R. Stan
    Structured and tuned array generation (STAG) for high-performance random logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:257-262 [Conf]
  3. Matthew M. Ziegler, Mircea R. Stan
    A Case for CMOS/nano co-design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:348-352 [Conf]
  4. Matthew M. Ziegler, Mircea R. Stan
    The CMOS/nano interface from a circuits perspective. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:904-907 [Conf]
  5. Zhenyu (Jerry) Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan
    Multi-Dimensional Circuit and Micro-Architecture Level Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:275-280 [Conf]
  6. Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler
    Hybrid CMOS/Molecular Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:703-708 [Conf]
  7. Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan
    Large-signal two-terminal device model for nanoelectronic circuit analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1201-1208 [Journal]

  8. The opportunity cost of low power design: a case study in circuit tuning. [Citation Graph (, )][DBLP]

  9. A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). [Citation Graph (, )][DBLP]

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