|
Search the dblp DataBase
Paul Zuber:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Paul Zuber, Armin Windschiegl, Raúl Medina Beltán de Otálora, Walter Stechele, Andreas Herkersdorf
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:986-987 [Conf]
- Paul Zuber, Florian Helmut Müller, Walter Stechele
Optimization Potential of CMOS Power by Wire Spacing. [Citation Graph (0, 0)][DBLP] GI Jahrestagung (1), 2005, pp:344-348 [Conf]
- Armin Windschiegl, Paul Zuber, Walter Stechele
Exploiting Metal Layer Characteristics for Low-Power Routing. [Citation Graph (0, 0)][DBLP] PATMOS, 2002, pp:55-64 [Conf]
- Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele
The Optimal Wire Order for Low Power CMOS. [Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:674-683 [Conf]
A holistic approach for statistical SRAM analysis. [Citation Graph (, )][DBLP]
Statistical SRAM analysis for yield enhancement. [Citation Graph (, )][DBLP]
Variability aware modeling of SoCs: From device variations to manufactured system yield. [Citation Graph (, )][DBLP]
Exponent Monte Carlo for Quick Statistical Circuit Simulation. [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.002secs
|