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Moritoshi Yasunaga: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroaki Kitano, Moritoshi Yasunaga
    Wafer Scale Integration for Massively Parallel Memory-Based Reasoning. [Citation Graph (0, 0)][DBLP]
    AAAI, 1992, pp:850-856 [Conf]
  2. Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
    A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:69-77 [Conf]
  3. Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara
    Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2000, pp:253-262 [Conf]
  4. Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara
    The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:116-125 [Conf]
  5. Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga
    A Fast Model-Building Method for Time Series Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:537- [Conf]
  6. Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim
    Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2000, pp:264-273 [Conf]
  7. Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
    Gene Finding Using Evolvable Reasoning Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:198-207 [Conf]
  8. H. Koizumi, T. Ochiai, T. Okahashi, Y. Yamashita, A. Maki, T. Yamamoto, Y. Inagami, H. Yoshizawa, M. Iwata, Takashi Omori, M. Yasunaga
    Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions. [Citation Graph (0, 0)][DBLP]
    ICONIP, 1998, pp:337-340 [Conf]
  9. Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yoshiki Yamaguchi
    On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:373-380 [Conf]
  10. Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara
    Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2001, v:2, n:3, pp:211-230 [Journal]
  11. Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
    An Online EHW Pattern Recognition System Applied to Face Image Recognition. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2007, pp:271-280 [Conf]
  12. Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
    An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:1-12 [Conf]
  13. Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga
    Variable length segmental-transmission-line and its parameter optimization based on GA. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:1576-1582 [Conf]
  14. Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim
    Finding transcriptional regulatory elements in Dictyostelium gene expression. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:1746-1752 [Conf]
  15. Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga, Akihiko Konagaya
    Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:48, n:3, pp:287-299 [Journal]

  16. The Segmental-Transmission-Line: Its Design and Prototype Evaluation. [Citation Graph (, )][DBLP]


  17. Bio-Inspired Functional Asymmetry Camera System. [Citation Graph (, )][DBLP]


  18. Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains. [Citation Graph (, )][DBLP]


  19. A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. [Citation Graph (, )][DBLP]


  20. Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. [Citation Graph (, )][DBLP]


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