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## Search the dblp DataBase
P. Glenn Gulak:
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## Publications of Author- Gennady Feygin, P. Glenn Gulak, Paul Chow
**Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.**[Citation Graph (0, 0)][DBLP] Data Compression Conference, 1993, pp:118-127 [Conf] - Gennady Feygin, P. Glenn Gulak, Paul Chow
**Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.**[Citation Graph (0, 0)][DBLP] Data Compression Conference, 1994, pp:254-263 [Conf] - Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak
**An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding.**[Citation Graph (0, 0)][DBLP] FCCM, 2004, pp:310-311 [Conf] - P. Glenn Gulak, Paul Chow
**A Field-Programmable Mixed-Analog-Digital Array.**[Citation Graph (0, 0)][DBLP] FPGA, 1995, pp:104-109 [Conf] - Kerry S. Lowe, P. Glenn Gulak
**Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:216-219 [Conf] - Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
**A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1945-1948 [Conf] - Kenneth J. Schultz, P. Glenn Gulak
**A Logic-enhanced Memory for Digital Data Recovery Circuits.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:2007-2010 [Conf] - P. Glenn Gulak
**A Review of Multiple-Valued Memory Technology.**[Citation Graph (0, 0)][DBLP] ISMVL, 1998, pp:222-231 [Conf] - Edward K. F. Lee, P. Glenn Gulak
**Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction.**[Citation Graph (0, 0)][DBLP] ISMVL, 1992, pp:208-215 [Conf] - Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu
**A Multiple-Valued Ferroelectric Content-Addressable Memory.**[Citation Graph (0, 0)][DBLP] ISMVL, 1996, pp:74-79 [Conf] - Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
**Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic.**[Citation Graph (0, 0)][DBLP] ISMVL, 1998, pp:264-269 [Conf] - David Gnaedig, Emmanuel Boutillon, Michel Jézéquel, Vincent C. Gaudet, P. Glenn Gulak
**On Multiple Slice Turbo Codes.**[Citation Graph (0, 0)][DBLP] Annales des Télécommunications, 2005, v:60, n:1-2, pp:79-102 [Journal] - Kenneth J. Schultz, P. Glenn Gulak
**Authors' reply to "A note on architectures for large-capacity CAMs".**[Citation Graph (0, 0)][DBLP] Integration, 1997, v:22, n:1-2, pp:173-176 [Journal] - Gennady Feygin, P. Glenn Gulak, Paul Chow
**Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.**[Citation Graph (0, 0)][DBLP] Inf. Process. Manage., 1994, v:30, n:6, pp:805-816 [Journal] - Vincent C. Gaudet, P. Glenn Gulak
**Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays.**[Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 1998, v:8, n:5-6, pp:541-558 [Journal] - G. E. Bridges, Werner Pries, Robert D. McLeod, M. Yunik, P. Glenn Gulak, Howard C. Card
**Dual Systolic Architectures for VLSI Digital Signal Processing Systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1986, v:35, n:10, pp:916-923 [Journal] - Howard C. Card, P. Glenn Gulak, Robert D. McLeod, Werner Pries
**(lambda,**[Citation Graph (0, 0)][DBLP]*T*) Complexity Measures for VLSI Computations in Constant Chip Area. IEEE Trans. Computers, 1987, v:36, n:1, pp:112-117 [Journal] - Kerry S. Lowe, P. Glenn Gulak
**A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:419-434 [Journal] - Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak
**Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes.**[Citation Graph (0, 0)][DBLP] IEEE Transactions on Communications, 2006, v:54, n:6, pp:1143- [Journal] - Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak
**Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes.**[Citation Graph (0, 0)][DBLP] IEEE Transactions on Communications, 2006, v:54, n:7, pp:1224-1234 [Journal] - Kenneth J. Schultz, P. Glenn Gulak
**Multicast contention resolution with single-cycle windowing using content addressable FIFO's.**[Citation Graph (0, 0)][DBLP] IEEE/ACM Trans. Netw., 1996, v:4, n:5, pp:731-742 [Journal] - Y. Eslami, Ali Sheikholeslami, P. Glenn Gulak, S. Masui, K. Mukaida
**An area-efficient universal cryptography processor for smart cards.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:43-56 [Journal] - Mahdi Shabany, P. Glenn Gulak
**Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:2295-2298 [Conf] - Mahdi Shabany, P. Glenn Gulak
**VLSI implementation of a sequential Monte Carlo receiver.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Mahdi Shabany, P. Glenn Gulak
**An efficient architecture for distributed resampling for high-speed particle filtering.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak
**Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:309-318 [Journal] **A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits.**[Citation Graph (, )][DBLP]**Scalable VLSI architecture for K-best lattice decoders.**[Citation Graph (, )][DBLP]**The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection.**[Citation Graph (, )][DBLP]**A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels.**[Citation Graph (, )][DBLP]**A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder.**[Citation Graph (, )][DBLP]
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