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Eero Aho:
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- Eero Aho, Jarno Vanne, Timo D. Hämäläinen
Parallel Memory Architecture for Arbitrary Stride Accesses. [Citation Graph (0, 0)][DBLP] DDECS, 2006, pp:65-70 [Conf]
- Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen
Enhanced Configurable Parallel Memory Architecture. [Citation Graph (0, 0)][DBLP] DSD, 2002, pp:28-37 [Conf]
- Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen
Block-level parallel processing for scaling evenly divisible frames. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1134-1137 [Conf]
- Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen
Comments on "Winscale: an image-scaling algorithm using an area pixel Model". [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:3, pp:454-455 [Journal]
- Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:7, pp:876-883 [Journal]
- Eero Aho, Jarno Vanne, Timo D. Hämäläinen
Parallel Memory Implementation for Arbitrary Stride Accesses. [Citation Graph (0, 0)][DBLP] ICSAMOS, 2006, pp:1-6 [Conf]
- Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna
Configurable implementation of parallel memory based real-time video downscaler. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2007, v:31, n:5, pp:283-292 [Journal]
A case for multi-channel memories in video recording. [Citation Graph (, )][DBLP]
Memory access characteristics of H.264 video encoder on embedded processor. [Citation Graph (, )][DBLP]
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